(VRV32I Load and Store Instructions
p0
ccopy_reg
_reconstructor
p1
(cvp_pack
Ip
p2
c__builtin__
object
p3
Ntp4
Rp5
(dp6
Vprop_count
p7
I8
sVname
p8
g0
sVprop_list
p9
(dp10
sVip_num
p11
I3
sVwid_order
p12
I3
sVrfu_dict
p13
(dp14
sVrfu_list
p15
(lp16
(V000_LB
p17
g1
(cvp_pack
Prop
p18
g3
Ntp19
Rp20
(dp21
Vitem_count
p22
I3
sg8
g17
sVtag
p23
VVP_IP003_P000
p24
sVitem_list
p25
(dp26
sg12
I0
sg15
(lp27
(V000
p28
g1
(cvp_pack
Item
p29
g3
Ntp30
Rp31
(dp32
g8
V000
p33
sg23
VVP_ISA_F003_S000_I000
p34
sVdescription
p35
Vlb rd, rs1, imm\u000ard = Sext(M[rs1+imm][0:7])\u000ard is calculated using signed arithmetic
p36
sVpurpose
p37
VISA\u000aChapter 2.6
p38
sVverif_goals
p39
VRegister operands:\u000a\u000aAll possible rs1 registers are used.\u000aAll possible rd registers are used.\u000aAll possible register combinations where rs1 == rd are used
p40
sVcoverage_loc
p41
Visacov.rv32i_lb_cg.cp_rs1\u000aisacov.rv32i_lb_cg.cp_rd\u000aisacov.rv32i_lb_cg.cp_rd_rs1_hazard
p42
sVpfc
p43
I3
sVtest_type
p44
I3
sVcov_method
p45
I1
sVcores
p46
I56
sVcomments
p47
V
p48
sVstatus
p49
g48
sVsimu_target_list
p50
(lp51
sg15
(lp52
sVrfu_list_2
p53
(lp54
sg13
(dp55
Vlock_status
p56
I0
ssbtp57
a(V001
p58
g1
(g29
g3
Ntp59
Rp60
(dp61
g8
V001
p62
sg23
VVP_ISA_F003_S000_I001
p63
sg35
Vlb rd, rs1, imm\u000ard = Sext(M[rs1+imm][0:7])\u000ard is calculated using signed arithmetic
p64
sg37
VISA\u000aChapter 2.6
p65
sg39
VInput operands:\u000a\u000aimmi value is +ve, -ve and zero\u000aAll combinations of rs1 and immi +ve, -ve, and zero values are used\u000aAll bits of rs1 are toggled\u000aAll bits of immi are toggled
p66
sg41
Visacov.rv32i_lb_cg.cp_immi_value\u000aisacov.rv32i_lb_cg.cp_rs1_toggle\u000aisacov.rv32i_lb_cg.cp_immi_toggle
p67
sg43
I3
sg44
I3
sg45
I1
sg46
I56
sg47
g48
sg49
g48
sg50
(lp68
sg15
(lp69
sg53
(lp70
sg13
(dp71
g56
I0
ssbtp72
a(V002
p73
g1
(g29
g3
Ntp74
Rp75
(dp76
g8
V002
p77
sg23
VVP_ISA_F003_S000_I002
p78
sg35
Vlb rd, rs1, imm\u000ard = Sext(M[rs1+imm][0:7])\u000ard is calculated using signed arithmetic
p79
sg37
VISA\u000aChapter 2.6
p80
sg39
VOutput result:\u000a\u000ard value is +ve, -ve and zero\u000aAll bits of rd are toggled
p81
sg41
Visacov.rv32i_lb_cg.cp_rd_value\u000aisacov.rv32i_lb_cg.cp_rd_toggle
p82
sg43
I3
sg44
I3
sg45
I1
sg46
I56
sg47
g48
sg49
g48
sg50
(lp83
sg15
(lp84
sg53
(lp85
sg13
(dp86
g56
I0
ssbtp87
asVrfu_list_1
p88
(lp89
sg53
(lp90
sg13
(dp91
sbtp92
a(V001_LH
p93
g1
(g18
g3
Ntp94
Rp95
(dp96
g22
I3
sg8
g93
sg23
VVP_IP003_P001
p97
sg25
(dp98
sg12
I1
sg15
(lp99
(V000
p100
g1
(g29
g3
Ntp101
Rp102
(dp103
g8
V000
p104
sg23
VVP_ISA_F003_S001_I000
p105
sg35
Vlh rd, rs1, imm\u000ard = Sext(M[rs1+imm][0:15])\u000ard is calculated using signed arithmetic
p106
sg37
VISA\u000aChapter 2.6
p107
sg39
VRegister operands:\u000a\u000aAll possible rs1 registers are used.\u000aAll possible rd registers are used.\u000aAll possible register combinations where rs1 == rd are used
p108
sg41
Visacov.rv32i_lh_cg.cp_rs1\u000aisacov.rv32i_lh_cg.cp_rd\u000aisacov.rv32i_lh_cg.cp_rd_rs1_hazard
p109
sg43
I3
sg44
I3
sg45
I1
sg46
I56
sg47
g48
sg49
g48
sg50
(lp110
sg15
(lp111
sg53
(lp112
sg13
(dp113
g56
I0
ssbtp114
a(V001
p115
g1
(g29
g3
Ntp116
Rp117
(dp118
g8
V001
p119
sg23
VVP_ISA_F003_S001_I001
p120
sg35
Vlh rd, rs1, imm\u000ard = Sext(M[rs1+imm][0:15])\u000ard is calculated using signed arithmetic
p121
sg37
VISA\u000aChapter 2.6
p122
sg39
VInput operands:\u000a\u000aimmi value is +ve, -ve and zero\u000aAll combinations of rs1 and immi +ve, -ve, and zero values are used\u000aAll bits of rs1 are toggled\u000aAll bits of immi are toggled\u000aUnaligned and aligned accesses from memory
p123
sg41
Visacov.rv32i_lh_cg.cp_immi_value\u000aisacov.rv32i_lh_cg.cp_rs1_toggle\u000aisacov.rv32i_lh_cg.cp_immi_toggle\u000aisacov.rv32i_lh_cg.cp_aligned
p124
sg43
I3
sg44
I3
sg45
I1
sg46
I56
sg47
g48
sg49
g48
sg50
(lp125
sg15
(lp126
sg53
(lp127
sg13
(dp128
g56
I0
ssbtp129
a(V002
p130
g1
(g29
g3
Ntp131
Rp132
(dp133
g8
V002
p134
sg23
VVP_ISA_F003_S001_I002
p135
sg35
Vlh rd, rs1, imm\u000ard = Sext(M[rs1+imm][0:15])\u000ard is calculated using signed arithmetic
p136
sg37
VISA\u000aChapter 2.6
p137
sg39
VOutput result:\u000a\u000ard value is +ve, -ve and zero\u000aAll bits of rd are toggled
p138
sg41
Visacov.rv32i_lh_cg.cp_rd_value\u000aisacov.rv32i_lh_cg.cp_rd_toggle
p139
sg43
I3
sg44
I3
sg45
I1
sg46
I56
sg47
g48
sg49
g48
sg50
(lp140
sg15
(lp141
sg53
(lp142
sg13
(dp143
g56
I0
ssbtp144
asg88
(lp145
sg53
(lp146
sg13
(dp147
sbtp148
a(V002_LW
p149
g1
(g18
g3
Ntp150
Rp151
(dp152
g22
I3
sg8
g149
sg23
VVP_IP003_P002
p153
sg25
(dp154
sg12
I2
sg15
(lp155
(V000
p156
g1
(g29
g3
Ntp157
Rp158
(dp159
g8
V000
p160
sg23
VVP_ISA_F003_S002_I000
p161
sg35
Vlw rd, rs1, imm\u000ard = Sext(M[rs1+imm][0:31])\u000ard is calculated using signed arithmetic
p162
sg37
VISA\u000aChapter 2.6
p163
sg39
VRegister operands:\u000a\u000aAll possible rs1 registers are used.\u000aAll possible rd registers are used.\u000aAll possible register combinations where rs1 == rd are used
p164
sg41
Visacov.rv32i_lw_cg.cp_rs1\u000aisacov.rv32i_lw_cg.cp_rd\u000aisacov.rv32i_lw_cg.cp_rd_rs1_hazard
p165
sg43
I3
sg44
I3
sg45
I1
sg46
I56
sg47
g48
sg49
g48
sg50
(lp166
sg15
(lp167
sg53
(lp168
sg13
(dp169
g56
I0
ssbtp170
a(V001
p171
g1
(g29
g3
Ntp172
Rp173
(dp174
g8
V001
p175
sg23
VVP_ISA_F003_S002_I001
p176
sg35
Vlw rd, rs1, imm\u000ard = Sext(M[rs1+imm][0:31])\u000ard is calculated using signed arithmetic
p177
sg37
VISA\u000aChapter 2.6
p178
sg39
VInput operands:\u000a\u000aimmi value is +ve, -ve and zero\u000aAll combinations of rs1 and immi +ve, -ve, and zero values are used\u000aAll bits of rs1 are toggled\u000aAll bits of immi are toggled\u000aUnaligned and aligned accesses from memory
p179
sg41
Visacov.rv32i_lw_cg.cp_immi_value\u000aisacov.rv32i_lw_cg.cp_rs1_toggle\u000aisacov.rv32i_lw_cg.cp_immi_toggle\u000aisacov.rv32i_lw_cg.cp_aligned
p180
sg43
I3
sg44
I3
sg45
I1
sg46
I56
sg47
g48
sg49
g48
sg50
(lp181
sg15
(lp182
sg53
(lp183
sg13
(dp184
g56
I0
ssbtp185
a(V002
p186
g1
(g29
g3
Ntp187
Rp188
(dp189
g8
V002
p190
sg23
VVP_ISA_F003_S002_I002
p191
sg35
Vlw rd, rs1, imm\u000ard = Sext(M[rs1+imm][0:31])\u000ard is calculated using signed arithmetic
p192
sg37
VISA\u000aChapter 2.6
p193
sg39
VOutput result:\u000a\u000ard value is +ve, -ve and zero\u000aAll bits of rd are toggled
p194
sg41
Visacov.rv32i_lw_cg.cp_rd_value\u000aisacov.rv32i_lw_cg.cp_rd_toggle
p195
sg43
I3
sg44
I3
sg45
I1
sg46
I56
sg47
g48
sg49
g48
sg50
(lp196
sg15
(lp197
sg53
(lp198
sg13
(dp199
g56
I0
ssbtp200
asg88
(lp201
sg53
(lp202
sg13
(dp203
sbtp204
a(V003_LBU
p205
g1
(g18
g3
Ntp206
Rp207
(dp208
g22
I3
sg8
g205
sg23
VVP_IP003_P003
p209
sg25
(dp210
sg12
I3
sg15
(lp211
(V000
p212
g1
(g29
g3
Ntp213
Rp214
(dp215
g8
V000
p216
sg23
VVP_ISA_F003_S003_I000
p217
sg35
Vlbu rd, rs1, imm\u000ard = Zext(M[rs1+imm][0:7])\u000ard is calculated using unsigned arithmetic
p218
sg37
VISA\u000aChapter 2.6
p219
sg39
VRegister operands:\u000a\u000aAll possible rs1 registers are used.\u000aAll possible rd registers are used.\u000aAll possible register combinations where rs1 == rd are used
p220
sg41
Visacov.rv32i_lbu_cg.cp_rs1\u000aisacov.rv32i_lbu_cg.cp_rd\u000aisacov.rv32i_lbu_cg.cp_rd_rs1_hazard
p221
sg43
I3
sg44
I3
sg45
I1
sg46
I56
sg47
g48
sg49
g48
sg50
(lp222
sg15
(lp223
sg53
(lp224
sg13
(dp225
g56
I0
ssbtp226
a(V001
p227
g1
(g29
g3
Ntp228
Rp229
(dp230
g8
V001
p231
sg23
VVP_ISA_F003_S003_I001
p232
sg35
Vlbu rd, rs1, imm\u000ard = Zext(M[rs1+imm][0:7])\u000ard is calculated using unsigned arithmetic
p233
sg37
VISA\u000aChapter 2.6
p234
sg39
VInput operands:\u000a\u000aimmi value is +ve, -ve and zero\u000aAll combinations of rs1 and immi +ve, -ve, and zero values are used\u000aAll bits of rs1 are toggled\u000aAll bits of immi are toggled
p235
sg41
Visacov.rv32i_lbu_cg.cp_immi_value\u000aisacov.rv32i_lbu_cg.cp_rs1_toggle\u000aisacov.rv32i_lbu_cg.cp_immi_toggle
p236
sg43
I3
sg44
I3
sg45
I1
sg46
I56
sg47
g48
sg49
g48
sg50
(lp237
sg15
(lp238
sg53
(lp239
sg13
(dp240
g56
I0
ssbtp241
a(V002
p242
g1
(g29
g3
Ntp243
Rp244
(dp245
g8
V002
p246
sg23
VVP_ISA_F003_S003_I002
p247
sg35
Vlbu rd, rs1, imm\u000ard = Zext(M[rs1+imm][0:7])\u000ard is calculated using unsigned arithmetic
p248
sg37
VISA\u000aChapter 2.6
p249
sg39
VOutput result:\u000a\u000ard value is +ve, -ve and zero\u000aAll bits of rd[7:0] are toggled
p250
sg41
Visacov.rv32i_lbu_cg.cp_rd_value\u000aisacov.rv32i_lbu_cg.cp_rd_toggle
p251
sg43
I3
sg44
I3
sg45
I1
sg46
I56
sg47
g48
sg49
g48
sg50
(lp252
sg15
(lp253
sg53
(lp254
sg13
(dp255
g56
I0
ssbtp256
asg88
(lp257
sg53
(lp258
sg13
(dp259
sbtp260
a(V004_LHU
p261
g1
(g18
g3
Ntp262
Rp263
(dp264
g22
I3
sg8
g261
sg23
VVP_IP003_P004
p265
sg25
(dp266
sg12
I4
sg15
(lp267
(V000
p268
g1
(g29
g3
Ntp269
Rp270
(dp271
g8
V000
p272
sg23
VVP_ISA_F003_S004_I000
p273
sg35
Vlhu rd, rs1, imm\u000ard = Zext(M[rs1+imm][0:15])\u000ard is calculated using unsigned arithmetic
p274
sg37
VISA\u000aChapter 2.6
p275
sg39
VRegister operands:\u000a\u000aAll possible rs1 registers are used.\u000aAll possible rd registers are used.\u000aAll possible register combinations where rs1 == rd are used
p276
sg41
Visacov.rv32i_lhu_cg.cp_rs1\u000aisacov.rv32i_lhu_cg.cp_rd\u000aisacov.rv32i_lhu_cg.cp_rd_rs1_hazard
p277
sg43
I3
sg44
I3
sg45
I1
sg46
I56
sg47
g48
sg49
g48
sg50
(lp278
sg15
(lp279
sg53
(lp280
sg13
(dp281
g56
I0
ssbtp282
a(V001
p283
g1
(g29
g3
Ntp284
Rp285
(dp286
g8
V001
p287
sg23
VVP_ISA_F003_S004_I001
p288
sg35
Vlhu rd, rs1, imm\u000ard = Zext(M[rs1+imm][0:15])\u000ard is calculated using unsigned arithmetic
p289
sg37
VISA\u000aChapter 2.6
p290
sg39
VInput operands:\u000a\u000aimmi value is +ve, -ve and zero\u000aAll combinations of rs1 and immi +ve, -ve, and zero values are used\u000aAll bits of rs1 are toggled\u000aAll bits of immi are toggled\u000aUnaligned and aligned accesses from memory
p291
sg41
Visacov.rv32i_lhu_cg.cp_immi_value\u000aisacov.rv32i_lhu_cg.cp_rs1_toggle\u000aisacov.rv32i_lhu_cg.cp_immi_toggle\u000aisacov.rv32i_lhu_cg.cp_aligned
p292
sg43
I3
sg44
I3
sg45
I1
sg46
I56
sg47
g48
sg49
g48
sg50
(lp293
sg15
(lp294
sg53
(lp295
sg13
(dp296
g56
I0
ssbtp297
a(V002
p298
g1
(g29
g3
Ntp299
Rp300
(dp301
g8
V002
p302
sg23
VVP_ISA_F003_S004_I002
p303
sg35
Vlhu rd, rs1, imm\u000ard = Zext(M[rs1+imm][0:15])\u000ard is calculated using unsigned arithmetic
p304
sg37
VISA\u000aChapter 2.6
p305
sg39
VOutput result:\u000a\u000ard value is +ve, -ve and zero\u000aAll bits of rd[15:0] are toggled
p306
sg41
Visacov.rv32i_lhu_cg.cp_rd_value\u000aisacov.rv32i_lhu_cg.cp_rd_toggle
p307
sg43
I3
sg44
I3
sg45
I1
sg46
I56
sg47
g48
sg49
g48
sg50
(lp308
sg15
(lp309
sg53
(lp310
sg13
(dp311
g56
I0
ssbtp312
asg88
(lp313
sg53
(lp314
sg13
(dp315
sbtp316
a(V005_SB
p317
g1
(g18
g3
Ntp318
Rp319
(dp320
g22
I3
sg8
g317
sg23
VVP_IP003_P005
p321
sg25
(dp322
sg12
I5
sg15
(lp323
(V000
p324
g1
(g29
g3
Ntp325
Rp326
(dp327
g8
V000
p328
sg23
VVP_ISA_F003_S005_I000
p329
sg35
Vsb rs1, rs2, imm\u000aM[rs1+imm][0:7] = rs2[0:7]
p330
sg37
VISA\u000aChapter 2.6
p331
sg39
VRegister operands:\u000a\u000aAll possible rs1 registers are used.\u000aAll possible rs2 registers are used.
p332
sg41
Visacov.rv32i_sb_cg.cp_rs1\u000aisacov.rv32i_sb_cg.cp_rs2
p333
sg43
I3
sg44
I3
sg45
I1
sg46
I56
sg47
g48
sg49
g48
sg50
(lp334
sg15
(lp335
sg53
(lp336
sg13
(dp337
g56
I0
ssbtp338
a(V001
p339
g1
(g29
g3
Ntp340
Rp341
(dp342
g8
V001
p343
sg23
VVP_ISA_F003_S005_I001
p344
sg35
Vsb rs1, rs2, imm\u000aM[rs1+imm][0:7] = rs2[0:7]
p345
sg37
VISA\u000aChapter 2.6
p346
sg39
VInput operands:\u000a\u000aimms value is +ve, -ve and zero\u000aAll bits of rs1 are toggled\u000aAll bits of rs2 are toggled\u000aAll bits of imms are toggled
p347
sg41
Visacov.rv32i_sb_cg.cp_imms_value\u000aisacov.rv32i_sb_cg.cp_rs1_toggle\u000aisacov.rv32i_sb_cg.cp_rs2_toggle\u000aisacov.rv32i_sb_cg.cp_imms_toggle
p348
sg43
I3
sg44
I3
sg45
I1
sg46
I56
sg47
g48
sg49
g48
sg50
(lp349
sg15
(lp350
sg53
(lp351
sg13
(dp352
g56
I0
ssbtp353
asg88
(lp354
sg53
(lp355
sg13
(dp356
sbtp357
a(V006_SH
p358
g1
(g18
g3
Ntp359
Rp360
(dp361
g22
I2
sg8
g358
sg23
VVP_IP003_P006
p362
sg25
(dp363
sg12
I6
sg15
(lp364
(V000
p365
g1
(g29
g3
Ntp366
Rp367
(dp368
g8
V000
p369
sg23
VVP_ISA_F003_S006_I000
p370
sg35
Vsh rs1, rs2, imm\u000aM[rs1+imm][0:15] = rs2[0:15]
p371
sg37
VISA\u000aChapter 2.6
p372
sg39
VRegister operands:\u000a\u000aAll possible rs1 registers are used.\u000aAll possible rs2 registers are used.
p373
sg41
Visacov.rv32i_sh_cg.cp_rs1\u000aisacov.rv32i_sh_cg.cp_rs2
p374
sg43
I3
sg44
I3
sg45
I1
sg46
I56
sg47
g48
sg49
g48
sg50
(lp375
sg15
(lp376
sg53
(lp377
sg13
(dp378
g56
I0
ssbtp379
a(V001
p380
g1
(g29
g3
Ntp381
Rp382
(dp383
g8
V001
p384
sg23
VVP_ISA_F003_S006_I001
p385
sg35
Vsh rs1, rs2, imm\u000aM[rs1+imm][0:15] = rs2[0:15]
p386
sg37
VISA\u000aChapter 2.6
p387
sg39
VInput operands:\u000a\u000aimms value is +ve, -ve and zero\u000aAll bits of rs1 are toggled\u000aAll bits of rs2 are toggled\u000aAll bits of imms are toggled\u000aUnaligned and aligned accesses to memory
p388
sg41
Visacov.rv32i_sh_cg.cp_imms_value\u000aisacov.rv32i_sh_cg.cp_rs1_toggle\u000aisacov.rv32i_sh_cg.cp_rs2_toggle\u000aisacov.rv32i_sh_cg.cp_imms_toggle\u000aisacov.rv32i_sh_cg.cp_aligned
p389
sg43
I3
sg44
I3
sg45
I1
sg46
I56
sg47
g48
sg49
g48
sg50
(lp390
sg15
(lp391
sg53
(lp392
sg13
(dp393
g56
I0
ssbtp394
asg88
(lp395
sg53
(lp396
sg13
(dp397
sbtp398
a(V007_SW
p399
g1
(g18
g3
Ntp400
Rp401
(dp402
g22
I2
sg8
g399
sg23
VVP_IP003_P007
p403
sg25
(dp404
sg12
I7
sg15
(lp405
(V000
p406
g1
(g29
g3
Ntp407
Rp408
(dp409
g8
V000
p410
sg23
VVP_ISA_F003_S007_I000
p411
sg35
Vsw rs1, rs2, imm\u000aM[rs1+imm][0:31] = rs2[0:31]
p412
sg37
VISA\u000aChapter 2.6
p413
sg39
VRegister operands:\u000a\u000aAll possible rs1 registers are used.\u000aAll possible rs2 registers are used.
p414
sg41
Visacov.rv32i_sw_cg.cp_rs1\u000aisacov.rv32i_sw_cg.cp_rs2
p415
sg43
I3
sg44
I3
sg45
I1
sg46
I56
sg47
g48
sg49
g48
sg50
(lp416
sg15
(lp417
sg53
(lp418
sg13
(dp419
g56
I0
ssbtp420
a(V001
p421
g1
(g29
g3
Ntp422
Rp423
(dp424
g8
V001
p425
sg23
VVP_ISA_F003_S007_I001
p426
sg35
Vsw rs1, rs2, imm\u000aM[rs1+imm][0:31] = rs2[0:31]
p427
sg37
VISA\u000aChapter 2.6
p428
sg39
VInput operands:\u000a\u000aimms value is +ve, -ve and zero\u000aAll bits of rs1 are toggled\u000aAll bits of rs2 are toggled\u000aAll bits of imms are toggled\u000aUnaligned and aligned accesses to memory
p429
sg41
Visacov.rv32i_sw_cg.cp_imms_value\u000aisacov.rv32i_sw_cg.cp_rs1_toggle\u000aisacov.rv32i_sw_cg.cp_rs2_toggle\u000aisacov.rv32i_sw_cg.cp_imms_toggle\u000aisacov.rv32i_sw_cg.cp_aligned
p430
sg43
I3
sg44
I3
sg45
I1
sg46
I56
sg47
g48
sg49
g48
sg50
(lp431
sg15
(lp432
sg53
(lp433
sg13
(dp434
g56
I0
ssbtp435
asg88
(lp436
sg53
(lp437
sg13
(dp438
sbtp439
asVrfu_list_0
p440
(lp441
sg88
(lp442
sVvptool_gitrev
p443
V$Id: af214b54d38e440023a14011aefff4dabfd5f5ad $
p444
sVio_fmt_gitrev
p445
V$Id: 052d0c6f3d12d7984d208b14555a56b2f0c2485d $
p446
sVconfig_gitrev
p447
V$Id: 0422e19126dae20ffc4d5a84e4ce3de0b6eb4eb5 $
p448
sVymlcfg_gitrev
p449
V$Id: 286c689bd48b7a58f9a37754267895cffef1270c $
p450
sbtp451
.